FX2 GPIF AC timing diagrams | Cypress Semiconductor
FX2 GPIF AC timing diagrams
My question is respect to the timing diagrams provided in section 9.6 of the Cypress CY7C68013 FX2 datasheet. Basically, for an internally sourced 48MHz IFCLK, are the numbers and picture with respect to IFCLK inside the device, or are they measured at the pin.
The reason I'm asking is that probing at the output pins of the FX2 I see that for example that the CTLx output is actually driven several nanosections *before* the rising edge at the IFCLK pin. IFCLK is not configured to be inverted and the number is no where near the spec'ed max clock to out of 6.7ns. Same issue with the GPIF address and the data lines.
Can anyone provide any clarity? Thanks,