FX2 Data Corruption | Cypress Semiconductor
FX2 Data Corruption
I'm experiencing some data corruption from the point I send data to the OUT endpoint and by the time it reaches the fdata pins on the slave FIFO. Let me explain my setup.
I started by following the Synchronous Slave FIFO Streaming Example. So I have an Altera MAX V CPLD acting as a Master FIFO and the FX2 configured as a Slave FIFO with two endpoints. Endpoint 0x02 is configured as an OUT BULK end point and 0x86 is configured as an IN INTERRUPT endpoint with polling interval of 1. You can see the descriptor here https://gist.github.com/ismell/9390416#file-dscr-asm-L95.
The FX2 is configured to auto commit both endpoints. I am using an external clock provided by the CPLD as the FIFO clock. The clock is running at 10MHz. You can see the configuration here https://gist.github.com/ismell/9390416#file-fx2-c-L205.
My application is based off the Streaming Example included in the SDK. It queues up a few async transfers on the IN endpoint and waits for the CPLD to send a packet. https://gist.github.com/ismell/9390416#file-form-cs-L1081 shows the BeginXfer call and https://gist.github.com/ismell/9390416#file-form-cs-L1156 shows the EndXfer call. This is all copied from the example and has not been changed.
The changes do start with analyzeFrameData at https://gist.github.com/ismell/9390416#file-form-cs-L1160. If the frame contains one of the specified commands I want to send a packet on the OUT endpoint. I'm using the synchronous API to do this. You can see my XferData call on the OUT endpoint here https://gist.github.com/ismell/9390416#file-form-cs-L1372. This is where the data corruption is happening. It doesn't happen all the time, but randomly. I have used my logic analyzer to sniff the fdata[7:0] pins on the FX2 to see what it is sending to my CPLD and there is usually one byte that is incorrect.
Does anyone see anything wrong with the way I'm using the API? Is using the synchronous XferData API wrong in this case? Should I be creating an async request for my OUT endpoint?
Any suggestions would be greatly appreciated.
p.s) I'm using an Interrupt IN endpoint because I need to keep latency as low as possible. I have under 1ms between the time the CPLD sends the pkt_end signal to the FX2 and when I have to start writing data back to the CPLD.