FIFO READ | Cypress Semiconductor
I am currently working on a project to get the video out of a camera using a FX2LP. I am trying to understand the FIFO read using GPIF. I have attached the FSYNC to RDY0 and LSYNC to RDY1. The hardware seems to work right as i able to receive the data out of the camera using a single read byte. I want to FIFO read waveform so that i can get the SYNC frame out of the camera and get the video out of the camera. But i still don't understand completely the transition from the timing diagrams to the state diagrams using GPIF. The following points, I am having confusion with:
1. In my project, FSYNC will rise at least one clock cycle before LSYNC. I want to make sure that FSYNC and LSYNC are both 0 before i activate the data. But if the decision state I can't use if FYSNC = 0 and LSYNC = 0 because the second data value is always 1.
2. What should i use for the transaction counter? i am receiving 1 byte per pixel and it is 320 x 240 camera. Should i use the transaction counter to be 76800? I am confused that should I get frame in each FIFO read transaction. If yes, i want to use the AUTO IN mode, will the data be transferred automatically once the data buffer filled with 512 bytes?
I am attaching the timing diagram of the camera. Can you suggest any what would be the best way for me to get the video out of the camera.
I would really appreciate if someone can help me with this issue.