Failing to get idle to assert in TD Poll | Cypress Semiconductor
Failing to get idle to assert in TD Poll
We are using the bulk loop fifo example with a few modifications with the cy7c68013a 56 pin FX2LP.
The states are as follows:
GPIO PA2 is used to reset the Cypress cy7c4245 4K word fifo and a FPGA
GPIO PA3 is used to arm the FPGA
The FPGA waits for a external trigger
Once triggered the FPGA drops /WEN and latches time stamps(2 words), antenna rotation count (1 word) in the first 3 words and 4093 ADC samples into the remaining FIFO space until fifo full (/FF) drops. This is all completed with the ADC 25MHz sample clock
The fpga raises WEN and signals done via PA3 to the FX2LP
This works very well.
Now the problem:
With EP6 configured as an endpoint we trigger the GPIF as a master and move the fifo data to the host but with a problem. If we do not configure our S3 state to lower /REN and /OE then REN toggles instead of staying low so we read the fifo on every 3rd or 4th IFCLK/FIFO RCLK so it takes 500us to empty the fifo but we get all of the data and not empty fifo (/EF) returns low (i.e. empty).
If we set IF /EF=1 AND /EF=1 go to S3 else go to idle and configure /WEN and /OE also using /EF we empty the fifo in an expected 85.3us (1/48MHz * 4096) and we see /FE go low as it should. But we do not get a GPIF idle, ( it is the blue highlighted line below) and hang.
Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
We have the RDY, CTL, /OE, IFCLK connected to /REN, /EF, RCLK, /OE correctly and we do drain the fifo.
I realize this is a bit sketchy. I'm hopeful someone has seen similar behavior before and has a suggestion or two where to look.