CY7C68013A stops to fill FIFO buffers randomly | Cypress Semiconductor
CY7C68013A stops to fill FIFO buffers randomly
I am using CY7C68013A with EP2 set up as iso OUT endpoint. The data from FIFO buffers is read by external synchronous master (CPLD). The problem is that at random times FLAGA output configured as actile low EP2 empty flag becomes zero, and stays acitve, while host continues sending data to EP2, until I reset the CY7C68013A and reload the firmware.
What can be the reason of such behavior?