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CY7C68013A : EZ-USB FX2 packet data is lost 512*N byte data | Cypress Semiconductor

CY7C68013A : EZ-USB FX2 packet data is lost 512*N byte data

Summary: 2 Replies, Latest post by aasi on 25 Feb 2011 05:08 AM PST
Verified Answers: 0
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shutech4's picture
1 post

Hi all,

I created the system that 4k byte data is transferred through EZ-USB bulk transfer. FPGA (target side) create 4k byte data created and host side received data.

But we sometimes found that EZ-USB FX2 packet data is lost 512*N byte data. And packet reading time is sometimes takes 100msec or more. (usual case average is 16-17msec)

EZ-USB FX2 has two 512 byte buffer that is used as FIFO. I guess to have it overwritten unexpectedly.

This same experience that someone for?

And how you resolved?


The following are the details.
FPGA: Actel APA-450-BG456
Driver: Windows almost as a sample using the Bulk Transfer
USB Target: 512byte * 2 FIFO memory used in

System Specifications
• USB Bulk Transfer
• Baud rate is about 2Mbps
• FPGA allows every 16msec burn data to create a 4K SRAM save nearly
• FPGA look at the USB Overflow flag Overflow if not designed to write data
• Host-side applications, a simple data earnestly Read

worrisome phenomenon
• The data of received at the host is 512*N bytes lost
• Read by the host, but sometimes time-consuming than the 100msec

Read the host side code
    h->overlappedIn.Internal = 0;
    success = ReadFile(h->handleIn,
    if (!success) {
        if ( GetLastError() != ERROR_IO_PENDING ) {
            DebugVal("ReadFile Error = %d", GetLastError(), DEBUG_LEVEL_ERR);
            return DEV_DEVICE_IO_ERROR;
    waitResult = WaitForSingleObject(h->overlappedIn.hEvent,timeOut);
    if (waitResult == WAIT_TIMEOUT) {
        DebugMsg("ReadFile Error = WAIT_TIMEOUT", DEBUG_LEVEL_ERR);
        return DEV_TIMEOUT;


JLEE's picture
1 post

I have similar if not exact setup and see the same intermittent errors.  Interested to see solution.

aasi's picture
Cypress Employee
1166 posts

What is the type of endpoint used? Is flow control used on the FPGA-FX2LP interface i.e. check if buffer is available before sending data.



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