The CY7C68003 stop a CLOCK signal after my first TX CMD | Cypress Semiconductor
The CY7C68003 stop a CLOCK signal after my first TX CMD
Hello! I am try to use CY7C68003 with my FPGA chip. Now I can say for CY7, what generator I use: I send the pulses on RESET, the CLOCK signal is begin - that is all right. After 10 pulses of CLOCK, whan the DIR signal is surely stay in '0', I sent my TX CMD. For simplicity I only write the register USB Interface Control, to run the work of port with current settings. I set the DATA bus into B5h (to write register 35h), wait the signal NXT='1' and set DATA=04h (to set bit UsbEnable to '1'). And then, after the falling edge of my STP signal, the CY7 stop generation of CLOCK. What I do incorrectly?