CTL0 counting with Logic analyzer is incorrect as GPIFTCBx. | Cypress Semiconductor
CTL0 counting with Logic analyzer is incorrect as GPIFTCBx.
I'm working witt CY7C68013A. It is transfer 2MB data to host.
EP6 is used as input endpoint.
In flow state, I've set as below.
DataXFER : Rising edge
Master strobe half period : 2
Flow logic : if(FIFOflag=1 and FifoFlag=1)
then CTL0 = 1;
else CTL0 = 0;
With Logic analyzer, I've counted CTL0 pin's signal.
It's last counting number is 1023999, not 1024000.
In host program , WaitForXfer() is return correctly within about 125msec.
in my think, 125msec is correct consumed time to transfer 2MB.
Ant the FinishDataXfer's inLen after function return is 1024000.
1. Why does Physical counting is differ to others?
2. Our memory will output data on falling edge of CTL0,
then MCU will get data on rising edge.
is it correct?
3. in my test, bulk speed for Read is 16MB/sec . but on other documents,
their circuit has about 40MB/sec.
I've attached working file.
SendCmd(VX_B3);//set GPIFTCBx as 1024000(0x0F_A000) and trigger GPIF
UCHAR *inContext = InEndpt->BeginDataXfer(inData,inlen,&inOvLap);
success = InEndpt->FinishDataXfer(inData,inlen, &inOvLap,inContext);
SendCmd(VX_B4);//vendor cmd. stop upload.
//Below is MCU code.
case VX_B3: // enable IN transfers
*EP0BUF = VX_B3;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
FIFORESET = 0x06; // reset EP6 FIFO
GPIFTCB3 = 0x00;
GPIFTCB2 = 0x0F;
GPIFTCB1 = 0xA0;
GPIFTCB0 = 0x00;
//read transaction & ep 6.
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO