Behavior of CTL0 is unexpected | Cypress Semiconductor
Behavior of CTL0 is unexpected
CTLx is configured as always high even idle mode(by GPIF Desinger). And FW do not intervene CTL0 when transaction data. However, the CTL0 will pull low for a few momont before launch GPIF fifo write transaction. I do not know what is the root cause about this behavior of CTL0.