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AN61345 violates timing | Cypress Semiconductor

AN61345 violates timing

Summary: 1 Reply, Latest post by Nick Xu on 23 Jan 2016 06:46 PM PST
Verified Answers: 0
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The aplication note proposes to react to a flag within a single cycle.

When I take the Clock to FLAGS output propagation delay of 9.5/13.5 ns how am I supposed to react to it within one period of 20.83 ns without violating the 18.7/12.7 ns setup time of SLRD or 10.4/12.1 ns of SLWR? As this is clearly not possible and I have not found a single implementation caring, what would be the correct way to implement it?

Also I couldn't find any information weather it is legal to assert SLRD while the FIFO is empty or SLWR while full. Can anyone point me to that information?

best regards

Nick Xu's picture
Cypress Employee
6 posts

Hi Markus,

Sorry for incorrect info about the timing, I'll check internally and let you know soon, please use the timings used in AN61345 FPGA projects for now.

Best Regards,


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