AN61345 violates timing | Cypress Semiconductor
AN61345 violates timing
The aplication note proposes to react to a flag within a single cycle.
When I take the Clock to FLAGS output propagation delay of 9.5/13.5 ns how am I supposed to react to it within one period of 20.83 ns without violating the 18.7/12.7 ns setup time of SLRD or 10.4/12.1 ns of SLWR? As this is clearly not possible and I have not found a single implementation caring, what would be the correct way to implement it?
Also I couldn't find any information weather it is legal to assert SLRD while the FIFO is empty or SLWR while full. Can anyone point me to that information?