AN61345 - Designing With EZ-USB® FX2LP™ Slave FIFO Interface | Cypress Semiconductor
AN61345 - Designing With EZ-USB® FX2LP™ Slave FIFO Interface
I have been working on the project provided with AN61345 application note (http://www.cypress.com/?rID=43046). The VHDL files and application notes are provided with the project.I am trying to create a top level and test bench file for the StreamIN, StreamOUT and Loopback.
The application note shows the hardware connection in figure 10 which is shown below.
I do not understand the use of PA1, PC0, PC1 signals?
On the documentation it says PC0 is used for synchronoizing the data trasnfers between the FPGA and FX2LP and PC1 is used to know the readliness of FPGA to supply the Slave FIFO interface clock (IFCLK). I had a look in Technical Ref. manual but it only talks about the pin connects of these 3 signals.
The VHDL code provided for StreamIN, StreamOUT and LoopBack does not mention PC0, PC1 and PA1 anywhere.
How and Where I should connect the PC0, PC1 and PA1 on the VHDL project document (Top Level & Test Bench)?