Aligned auto-discard packets on full FIFO | Cypress Semiconductor
Aligned auto-discard packets on full FIFO
Using an FX2LP...
I'm working on a project that is continuously filling the endpoint FIFO through an externally clocked GPIF interfaced data source. It's fairly high bandwidth (~10MBytes/sec) so I'm using 1024 byte quad-buffering and isochronous trnasfers (1-2 packets/uframe).
Periodically the host will not be able to keep up with the data rate and will fail to issue transfer requests for every frame. This is something I expect and do not consider it "the problem" because I am trying to make this device work on the slowest single-board computers I can manage.
Also, for the nature of the data I am streaming, it does not matter very much at all if I drop packets. What is 100% critical is that I maintain data alignment.
For example, if I consider the original data stream from the external device, I need to ensure that the first byte I read from it ends up in the first byte of the transfer. I need to ensure that the 1024th byte from the device ends up in the 1024th byte of the stream ... the 2048th byte ends up in the 2048th byte of the output stream, etc, etc. If I happen to drop a packet somewhere then I simply need to know that I failed to transfer 1024 bytes and insert 1024 bytes of zeros (or noise) in their place.
The issue that I'm having is, using AUTOIN, when the host gets behind and I commit the 4th output packet, the FIFO buffer goes full and the GPIF device stops writing to it. When the host finally gets around to clearing the buffer and the GPIF can once again begin writing to the FIFO buffer, the data stream is no longer aligned. The FULL flag certainly won't be cleared 1024, 2048, etc. bytes later to stay aligned.
What I would like is the following behavior:
When the 4th packet is committed to the USB domain, the 1st packet awaiting transmission is discarded to make room for another packet. It needs to behave such that not even a single byte from the GPIF device is discarded on a full buffer. I would be even fine if the entire USB buffer was cleared when full (discarding 4 packets) as long as the very next byte from the GPIF device can make it into a FIFO.
Anyone have an idea on how to produce or closely approximate this behavior?
Thanks for reading and for any help.