about cy68013A oddness | Cypress Semiconductor
about cy68013A oddness
I am interfacing the Cypress EZ-USB FX2LP (Cy7C68013A) to a Lattice FPGA. The data is transferred from FPGA through the slave FIFO interface in AUTOIN mode (auto-commit with size of 1024-byte) to PC.
Endpoint 2 is used, the fifo uses double buffering with packet size of 1024 bytes. The external interface is set to 16 bits wide. The interface clock IFCLK is driven by the FPGA, and is inverted internally in the FX2 (through IFCONFIG setting). Clock frequency is 48 MHz. Initialization of the endpoint buffer is performed as directed by the example provided in the EZ-USB technical reference manual.
The observed behavior is that, PC is waitting for data of usb ,when a 2048-byte packet is pushed to the slave fifo interface, it is tansferred to the USB domain and read by the PC. After two packets is read, the FX2 reports that the FIFO is not empty.At that point reading EP2FIFOBCH:L reports that the FIFO contains 62 bytes of data, which was never explicitly pushed to the slave fifo by the FPGA.
Has anyone encountered problems like this before, and has he been able to solve them?
I would appreciate any help.