16-bit SLAVE FIFO bandwidth sharing scheme | Cypress Semiconductor
16-bit SLAVE FIFO bandwidth sharing scheme
I am using 68013A's 16-bit Slave FIFO to communicate with an FPGA. I have two continous data stream between the PC and the FPGA via 68013A. EP2 is configured as quad buffered BULK OUT, and EP6 is configured as quad buffered BULK IN. To share the use of the FIFO's data bus, I will need to switch the FIFO ADDR between EP2 and EP6 constantly, can I switch the FIFO ADDR from EP6 (BULK IN) to EP2 (BULK OUT) regardless of whether the data in EP6 have been committed or not?