Using SPI to configure FPGA and then enable 32-bit Slave FIFO | Cypress Semiconductor
Using SPI to configure FPGA and then enable 32-bit Slave FIFO
From the application mode of "Programming EZ-USB® FX3™ Processor Port as Synchronous Slave FIFO", 32 Bit data bus width is not supported if SPI is selected. After bootup, I use SPI (GPIO - SPI_SCK and GPIO - SPI_MOSI) to configure FPGA, then I enable GPFI to 32-bit slave FIFO mode, it is obviously doable. During firmware runtime, I want to re-configure FPGA with SPI interface again, but at that monent, GPIF is 32-bit slave FIFO mode, Can I stop GPIF or switch to 16-bit mode, using SPI re-configure FPGA, and swtich to 32-bit slave FIFO again?