Using GPIF II to configure FPGA then switch to slave FIFO | Cypress Semiconductor
Using GPIF II to configure FPGA then switch to slave FIFO
I am trying to understand if it is possible to configure an FPGA using GPIF II (32-bit slave selectMAP) which requires the GPIF be configured as Master mode. Then switch GPIF to slave FIFO mode. I am wondering if you have an example.
Based on my understanding, in my case I cannot have disjoint state machines because one is master and one is slave. So, if I define two separate GPIF II projects, how I should configure the chip after completing the FPGA configuration? At the moment when I load a firmware to cypress, I cannot load any other firmware until a power down then up happens.
Also, I need to have an enable/disable signal along with the data path to implement a non-continuous FPGA configuration. If I choose any available GPIO, will it be synchronze with the data (for instance, it will be working with PCLK = 80MHz rate)?