Uninterrupted data flow between FPGA and GPIF port. | Cypress Semiconductor
Uninterrupted data flow between FPGA and GPIF port.
In my application I have a FPGA connected to the GPIF port of the FX3 device. I want to have an uninterrupted data flow between the FPGA and FX3 (data to send to the host) and I understood that I need to use two GPIF sockets to switch between buffers without latency.
I want :
- use the FIFO write configuration to have the possibility to switch sockets with the A0-A1 address lines,
- use the DMA AUTO mode to maximize throughput ,
- only one IN end point.
So, my questions are :
- first of all, is that the right way ?
- and, can I use only one channel of the DMA mechanism (and this is it that changes automatically between socket) or I have to use the DMA multi-channel mechanism to transfer data from the two GPIF sockets to my IN end point ?