Unable to Start a GPIF Read from DMA in GPIF Master Mode | Cypress Semiconductor
Unable to Start a GPIF Read from DMA in GPIF Master Mode
I am working on a Master GPIF based project and I have ½ working(Transmits) but I can not get the second half to work(Reads) and need some help.
Right now, when the PC wants to read data from the FPGA, the host sends a Vendor Setup packet with the command in the packet. The FX3 parses this data and it sends the Read command data and length to the FPGA using a CyU3PGpifWriteDataWords() command and this works and is seen on a Logic Analyzer. When the FPGA sees this command, it asserts RD_RDY_N back to the FX, again seen on a Logic Analyzer. But the GPIF stops right here.
My GPIF state machine is now waiting in my RD_WAIT4DMA for DMA_RDY_TH0 to start transferring the data (see attachment). The data I am requesting is only a single word in this case with a 32 bit GPIF bus. I have tried to follow the GPIF Master Example on this site, but it’s not quite the same as what I have here. The question I have is “how do I force the DMA_RDY_TH0 signal to assert so I can advance to next state”? I have tried different versions of CyU3PDmaChannelSetXfer but I am stuck here and I can not figure out what I am doing wrong.