U1/U2 exit latencies in BOS descriptor (SS) | Cypress Semiconductor
U1/U2 exit latencies in BOS descriptor (SS)
After looking through the Cypress example projects distributed with the FX3 SDK, it seems that every BOS descriptor has values of 0 for U1 exit latency and U2 exit latency. I also don't see any specs for these in the FX3 datasheet (though maybe I missed it?)
Why are these values set to 0 in the SuperSpeed BOS descriptor? (last 3 bytes). Are they really so close to zero that this is accurate? Is zero a special value?