Two questions regarding AN65974 (Sync Slave FIFO) | Cypress Semiconductor
Two questions regarding AN65974 (Sync Slave FIFO)
Summary: 3 Replies, Latest post by DavidAustin on 11 Aug 2013 08:11 PM PDT
Verified Answers: 0
12 Dec 2012 08:57 AM PST#1
- The GIPF2 Designer project that comes with the AN has a suspicious-looking state called 'DSS_STATE' which seems to be an exact copy of the 'IDLE' state with exactly the same transition equations to other states. In addition to that, the transition equation that causes IDLE -> DSS_STATE also causes DSS_STATE -> IDLE. The related Designer project 'sync_slave_fifo_2bit.cyfx' from the 1.2.1 SDK does the same, whereas earlier versions didn't. What's the purpose of this DSS_STATE? Is it necessary (the 5-bit example doesn't have it) ?
- The documents describing the synchronous slave FIFO interface mention signal SLCS# all over the place but never clearly define if it is necessary at all: the state-machine works just the same if it is kept active (wired to low) all of the time (i.e. this signal may be removed from all transition equations without any behavioural changes), at no point is a SLCS# = 1 condition mentioned, and I can't find any explicit relation to FX3 hardware. My understanding is that I can get rid of this signal and may use GPIO for other purposes (f.e. use it as an output pin). Is this true? I'm asking because I have to use 32bit sync slave FIFO with I2C and UART in our application and I am running out of GPIOs.
Thanks in advance for looking into this!