You are here

transfer data | Cypress Semiconductor

transfer data

Summary: 2 Replies, Latest post by 1065271400_2323246 on 21 May 2017 08:09 PM PDT
Verified Answers: 0
Last post
Log in to post new comments.
1065271400_2323246's picture
User
33 posts

hello,everyone, 

Now I have a question, my data is cycling from 00 to FF,8 bit data,but  received data in the control center ,the first number isnt 00,it is a random number among the 00-FF,the last number is the previous number of  the first number,Is it because I dont distribute the address?

    I attached the control center,you will understand me when you see it .

regards,

Alex 

mady's picture
Cypress Employee
1093 posts

Hi,

Can you please analyse your control and data lines and verify that the FPGA (or any other device connnected to GPIF) gives the signals with proper timing? i.e, the SLWR starts asserting at 00 and stops at FF? (also check the behavior of the PKTEND signal.

Regards,

- Madhu Sudhan

1065271400_2323246's picture
User
33 posts

ok,thank you ,Madhu Sudhan,I will try it , I just  wonder ,now that, the control center can show the right data ,it means my fx3 is right?Because I am not familiar with the FX3 ,I am afraid it is because my fx3 is wrong ,so I want to confirm it ,thank you !

regards,

Alex 

Log in to post new comments.