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Timing running FX3 GPIF2 @ 100MHz | Cypress Semiconductor

Timing running FX3 GPIF2 @ 100MHz

Summary: 1 Reply, Latest post by Madhu Sudhan on 02 Aug 2015 12:00 PM PDT
Verified Answers: 0
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user_436851778's picture
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I'm currently designing a FPGA (Altera Cyclone V) core connected to the GPIF2 interface.

Unfortunately I couldn't constraint my design that it is running at maximum frequency of 100MHz.

Especially the CTL hold time of 0 ns is generating failing hold time violations.


Could somebody successfully connection an Altera FPGA to the FX3 GPIF2 interface and

running that interface @ 100MHz ?


Any comment is welcome.




mady's picture
Cypress Employee
963 posts


The altera Cyclone 3 FPGA has been interfaced with FX3 DVK at 100 MHz and the project (both FX3 firmware and FPGA project) are available here


-Madhu Sudhan

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