there is data losing when using external clock in master mode | Cypress Semiconductor
there is data losing when using external clock in master mode
I met a weird problem. I'm using FX3 GPIFII master mode to transfer data from USB to FPGA. When I use internal clock, all data can be received. However, when I use external clock (from FPGA) on USB3.0, some data was lost from FX3 to FPGA. And if I use external clock and USB2.0, no data was lost. Since I need to write data to DDR2, I need to write data through DCFIFO, and DCFIFO needs write clock and read clock are inherited from one clock source. Thus I have to use external clock on GPIFII.
Any one has comment? Thanks!