Synchronous Slave FIFO Thread Addressing | Cypress Semiconductor
Synchronous Slave FIFO Thread Addressing
We have a synchronous slave fifo set up and running at 40 MHz, with the active thread selected by the A0 and A1 pins.
It seems that when starting the state machine in the RESET state, writes will always go to thread 0, even if the address pins say, for example, thread 2. Once pktend asserts for the first time, though, the write will start going to the correct thread as specified by the pins.
We have found that by starting the state machine in IDLE, however, the first write goes to the correct thread as it should.
What is different about the RESET state such that it does not work properly, while IDLE does?