Synchronous slave FIFO stopped with full flag | Cypress Semiconductor
Synchronous slave FIFO stopped with full flag
I 've tested FX3 + FPGA board in 32bit GPIF II sync slave mode.
first, I tested the code GPIF II designer generate,
the step I did is
CyU3PPibInt, CyU3PGpifInitTransFunctions, CyU3PGpifWaveformLoad, CyU3PGpifConfigure, CyU3PGpifSMStart.
but this code did not work. so I use CyU3PGpifRegisterConfig function in SlaveFifoSync samplecode with 32bit setting.
later setting seems to work anyway, but after few second transfer is halted with FLAGA is low,
at this time PC generate NtStatus code 0xC0000001 :
1. What is the meaning NtStatus is 0xc0000001 ?
2. If I use partial flag mode, which setting I shoud change in slavefifosync sample?
3. In Synchronous write cycle timing chart, write operation seems to be stoped immediately as soon as FLAG is on(full).
I wonder if write operations after the FLAG is on affect some effect on FIFO.