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Synchronous slave FIFO stopped with full flag | Cypress Semiconductor

Synchronous slave FIFO stopped with full flag

Summary: 8 Replies, Latest post by 3211 on 01 Mar 2012 02:38 AM PST
Verified Answers: 0
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hcshin's picture
14 posts

Hello, members

I 've tested FX3 + FPGA board in 32bit GPIF II sync slave mode.

first, I tested the code GPIF II designer generate,

the step I did is

CyU3PPibInt, CyU3PGpifInitTransFunctions, CyU3PGpifWaveformLoad, CyU3PGpifConfigure, CyU3PGpifSMStart.

but this code did not work. so I use CyU3PGpifRegisterConfig function in SlaveFifoSync samplecode with 32bit setting.

later setting seems to work anyway, but after few second transfer is halted with FLAGA is low,

at this time PC generate NtStatus code 0xC0000001 :


contexts[i] = EndPt->BeginDataXfer(buffers[i], len, &inOvLap[i]);
if (EndPt->NtStatus || EndPt->UsbdStatus) // BeginDataXfer failed
           Display(String::Concat("Xfer request rejected. NTSTATUS = ",EndPt->NtStatus.ToString("x")));

1. What is the meaning NtStatus is 0xc0000001 ?

2. If I use partial flag mode, which setting I shoud change in slavefifosync sample?

3. In Synchronous write cycle timing chart, write operation  seems to be stoped immediately as soon as FLAG is on(full).

 I wonder if  write operations after the FLAG is on affect some effect on FIFO.


Best Regards,


hcshin's picture
14 posts

I use 26MHz OSC. and PCLK is 100MHz.

gopv's picture
Cypress Employee
20 posts

Nstatus 0xc0000001 means STATUS_UNSUCCESSFULL

user_156124105's picture
8 posts

Hi,hcshin,I have meet the same problem in my work,is this solved?If so ,could you help me ,my email is,thanks

3211's picture
13 posts

I have meet the same problem in my work,is this solved?

Lumpi6's picture
341 posts


is this post solved?

I meet the same problems how can I solve it? Is in this case the host side not available with free buffer, that the auto DMA channel can not switch to the next buffer? Or what else can happen?

Mostly I meet this problems on NEC/Renesas USB3 chipset. On a VIA or a onboard AMD USB3 chipset that does not happens so often.

aasi's picture
Cypress Employee
1166 posts

What are your hardware setting? PCLK frequency, bus width etc

This issue was there when 100MHz is used but the release version fixed the same.



Lumpi6's picture
341 posts

Hi Anand,

I have a FPGA connected to the FX3 GPIF II interface.

I were using different PCLK frequencies but now staying at 50, 80 or 100 MHz. Trying different if it works better or ...!

I am using the new Release version from cypress's software download and the chip is revision D (not ES)!




3211's picture
13 posts

when I set the DMA  PtoU is the AUTO MODE,some time later the Synchronous slave FIFO stopped with full flag.If I set the DMA PtoU is the Manual mode,the full flag is normal.Who can answer my question?Thinks

 apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSlFifoPtoU,
      CY_U3P_DMA_TYPE_AUTO, &dmaCfg);   //set auto mode for improving the speed ,but maybe device will stop

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