Synchronous Slave FIFO callback question | Cypress Semiconductor
Synchronous Slave FIFO callback question
Hi, I’m trying to use your slave fifo GPIF firmware demo for streaming data from an FPGA to a host PC.
At a first attempt I’m only interested on measuring the maximum device to host transfer bandwidth.
We used the GPIF designer to configure the GPIF interface for synchronous slave fifo with a 32 bit dada bus width.
On the FPGA we set (fixed):
SLOE set to 1 // no GPIF read
SLCS set to 0 // GPIF is always selected
SLWR set to 0 // continuous write
SLRD set to 1 // no read
PKEND set to 1 // only 1024 byte packets
ADRESS set 00 // only thread 0
We verified that the above listed signals have the correct logical value on the FX3 pins and we would expect to measure the maximum (device to host) transfer bandwidth using your sinch.Slave fifo example together with your streaming application… but… nothing happens.After a first short period where flagA is reporting “FIFO not full” once it get FULL it simply stops.It seems that CyFxSlFifoPtoUDmaCallback is newer called to forward the data to EP1 as we would expect.
Any suggestion about this?
Considering the value of the signals of interest presented above, would you expect your synchronus slave fifo example to work correctly?
Thanks in advance