Sync slave FIFO state machine crash? | Cypress Semiconductor
Sync slave FIFO state machine crash?
We are streaming video via a GPIF sync_slave_fifo_2bit interface, with FLAGA defined as Thread 0 DMA Ready and FLAGB defined as Thread 0 DMA Watermark. The watermark is set to 2 with no bursting, resulting in FLAGB leading FLAGA by 4 clocks.
We have noticed that whenever the FX3 negates FLAGB on the same clock edge as the video generator negates SLWR# for a line blanking interval, the FX3 never reasserts FLAGB again. This is true even after we send an additional beat of data to correct for the difference between the 3-cycle FLAGA latency and the 4-cycle FLAGB configuration.
In probing the FX3 registers while in this FLAGA asserted / FLAGB negated state we see the following:
"Socket has gone inactive within a DMA Transfer" (CY_U3P_PIB_PIB_ERR_CODE_TH0_SCK_ACTIVE)
"statemachine has transitioned to an invalid state" (CY_U3P_PIB_GPIF_ERR_CODE_INVALID_STATE_ERROR)
...and the GPIF state machine in IDLE state.
Has anyone experienced similar issues, or know what conditions trigger these error codes?