State of I/O pins during boot and reset | Cypress Semiconductor
State of I/O pins during boot and reset
My project requires the use of most all GPIO to be configured as general purpose I/O to control motors, solenoids, etc.. I need to know what state these I/O pins will be after initial power up, during the boot process, during an extended reset (reset active for a period of time), and the time before the GPIO interface is configured and enabled. Are all pins tri-stated, do the default to some known state other than tri-state? Where do I find this information?
Also, the data sheet states "All I/Os can be driven at full-strenght, three-quarter strength, half-strength, or quarter-strength. These drive strengths are configured separately for each interface." I cannot find how to configure the drive strength. Only thing I found is that output highs are pulled up through 50K and lows are pulled down through 10K resistors. Where can I find this information?