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small break time between DMA buffer switching of a certain thread | Cypress Semiconductor

small break time between DMA buffer switching of a certain thread

Summary: 3 Replies, Latest post by Chris R. on 03 Jul 2013 06:09 AM PDT
Verified Answers: 1
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jtzheng's picture
8 posts

Cypress doc says that there's a small break time when a certain thread switches its DMA buffer (not switching socket of the thread, but switching to next DMA buffer of the socket), how long is that time roughly? less than 1us or several micro-seconds or more?

Seems this is a difference from the FX2 chip, for FX2, there's no break time when crossing the USB FIFO buffer (e.g. for 4x 512bytes FIFO)...understood that FX3 needs more complicated design (DMA involved), but is there any idea about this breaking time?




aasi's picture
Cypress Employee
1166 posts

It is around 550 - 900ns. Considering auto mode. In manual mode it would have dependency based on what the application firmware is doing.

You can use the many to one configuration is one way of working around the buffer switching issue.



jtzheng's picture
8 posts



   The programming manual said 550 - 900 ns (in chapter about PPort)..,,there's another application notes about UVC said the break time is in "micro-seconds".

    550-900ns is good enough for my application.. Thanks again.



Chris R.'s picture
143 posts

In my application I use AUTO DMA and double buffering. But I can watch breaks up to 12µs while switching the DMA buffer. The minimum I can measure is 2.1µs. This results in a data rate of only 308MB/s using the 100MHz PCLK. Can you explain this? I use the SDK version 1.2.3

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