SlaveFIFO 32 bit error | Cypress Semiconductor
SlaveFIFO 32 bit error
I am using FX3 as a Device controller used for USB3.0 communication with PC. I'm interfacing an FPGA xilinx Spartan6 to the FX3 with the slave fifo 32 bit by GPIG II following the the guide of the website. For testing communication I'm using the loopback example of AN65974 downloaded folder and I custmoized the GPIF for my board with the GPIF tool . With the USB Control Center I stream data to the FPGA and it write back to the fifo correctly (I can watch them with chiscpope analyzer). Something fails in the communication from fx3 to pc. In the the attached file you can see the error in the 4th byte of 3rd line, 5th line, 7th line and so on.
Each line of the GPIO are right routered to the FPGA and equalized, I don't think there are problem with signal integrity. The hardware it seems ok.
Could you help me please?
thanks a lot