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Slave FIFO loopback transfer problem | Cypress Semiconductor

Slave FIFO loopback transfer problem

Summary: 1 Reply, Latest post by Madhu Sudhan on 08 Apr 2015 03:03 AM PDT
Verified Answers: 0
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ZoeWang's picture
10 posts


I'm working with the FX3 DVK, following the application notes AN65974 to perform stream_in, stream_out and loopback transfer with my Xilinx FPGA. When performing stream_in and stream_out transfer, it seems quite ok.

However, during loopback transfer, after transfer data out, when I was trying to read data back from bulk in endpoint, it shows that zero length data transfered. I think the communication betwwen FX3 and FPGA failed. So I tried to capture how each control signal data react from FPGA side during transfer. I found that my flagd is always 1 and never changed to 0 and my flagc once changed from 0 to 1, never changed back to 0. As a result, SLRD# keeps asserted during the whole process. Btw, I used the firmware code provided by Cypress and the flag configuration is just same.

How can I solve this problem?





mady's picture
Cypress Employee
964 posts


If you are getting a ZLP it means the PKTEND signal is kept asserted (low) for some reason. Can you please probe that pin and confirm?


-Madhu Sudhan



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