Slave FIFO loopback problems | Cypress Semiconductor
Slave FIFO loopback problems
I'm working with the FX3 SuperSpeed Explorer Kit to try and send data to (and receive data from) an FPGA. I'm new to wkring with USB controllers, and I'm not really a sofware engineer, so I looked at AN65974, and I found that the LOOPBACK example works with my needs with a few edits. Using their loopback mode, I tried to separated the read and write sequences so they operate independently from each other but in such a way that the loopback function can still occur.
Working with a 100 MHz clock coming from the FPGA, I am trying to perform a loopback operation. I feel if I can implement the separation of the processes correctly, I can loop the data back normally. However, when I perform the loopback sequence, the data I receive is not the data I sent out. I'm working with a USB 2.0 connection, since I don't have access to a USB 3.0 port, and I'm sending 512 B of data out at one time. I'm not sure whether it is a firmware problem, but this also occurs with the original project posted by Cypress with their firmware. Any suggestions on how to solve this?
If it helps, according to Cypress, when initialized, the flags should be: FLAG A = FLAG B = HIGH, FLAG C = FLAG D = LOW.
However, Flag D, which is configured to be a DMA watermark flag for a thread, is HIGH. Could this cause problems with transfer accuracy?