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Question for design

Summary: 2 Replies, Latest post by RickL on 20 Dec 2013 01:49 PM PST
Verified Answers: 0
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RickL's picture
25 posts



My goal is to do short data transfers between the FX3 and an altera FPGA using the GPIF II bus. (packet sizes would be ~100bytes). Fx3 would be master.

I was thinking doing a state machine that does the handshake based on the DMA_RDY_TH0 condition, and comes back to idle on the DMA_WM_TH0 condition.

if I do this, can I then just send data form the PC to the FX3 on the BulkInEnd port ? would this trigger the DMA_RDY_TH0 condition ? 



scutifer's picture
Cypress Employee
134 posts

 You'd send data on an OUT endpoint to the FX3 and receive data from an IN endpoint from FX3. So, you'd use device.BulkOutEndPt.


Regarding the GPIF II design, you can just use DMA_RDY_TH0 as the triggers aren't subjected to the same latency constraints as the flags are.

When you send data from the PC to FX3 (and if a channel exists between PIB socket 0 and a USB producer socket), the DMA_RDY_TH0 trigger will be set to '1' indicating that data is available to be written out. And when the buffer is drained out, DMA_RDY_TH0 will fall to '0'.

So, you can initiate writes on DMA_RDY_TH0 and stop on !DMA_RDY_TH0.


RickL's picture
25 posts

 thanks scutifer :)

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