Question for design | Cypress Semiconductor
Question for design
My goal is to do short data transfers between the FX3 and an altera FPGA using the GPIF II bus. (packet sizes would be ~100bytes). Fx3 would be master.
I was thinking doing a state machine that does the handshake based on the DMA_RDY_TH0 condition, and comes back to idle on the DMA_WM_TH0 condition.
if I do this, can I then just send data form the PC to the FX3 on the BulkInEnd port ? would this trigger the DMA_RDY_TH0 condition ?