PWM signal behaviour is not predictable | Cypress Semiconductor
PWM signal behaviour is not predictable
I configured one GPIO pin as PWM signal by using API call CyU3PGpioSetComplexConﬁg. Measured signal waveform was different to program code. It seems threshold value was not set, so PWM signal was half the frequency with a duty-cycle of 50%.
To check behaviour I used following program code:
volatile uint32_t period = 100800;
volatile uint32_t threshold = 1000;
DBG_INFO_VALUE("thershold = ", threshold);
status = CyU3PGpioComplexUpdate (FX3_FPGA_TRIG_FX3, threshold, period - 1);
threshold += 1000;
if (threshold > period)
threshold = 1000;
I expect to see a PWM signal with increasing duty-cycle. Duty-cycle never become equal or greater than 100% and when close to 100% duty-cycle “jumps” back to nearly 0%. PWM frequency is 1kHz.
--> Measured signal is different: Duty-cycle is increasing and then decreasing.
For lower PWM frequency (1Hz to 10Hz?) it seems there is a problem with very small or very large duty cycles. These values are not “excepted”, signal stays low or high.
And as last point, it seems not possible to define start value for a PWM signal. This means it seems signal is inverted!
Did someone run into the same problem?