Problems reading whole packet from fx3 slave fifo design. | Cypress Semiconductor
Problems reading whole packet from fx3 slave fifo design.
I have problems with reading data from the GPIF with my FPGA design. The firmware on the FX3 is the synchronous slave fifo example with 2bit address bus. If I try to read the whole buffer in one burst cycle I never get the whole data. There are always five to eight read cycles missing, depending on the received packet size. After some time and in a second read attempt I get the rest of the data. Do you have an idea, how i can get the full packet data in a single burst read?