problem about flagb | Cypress Semiconductor
problem about flagb
The data is transferred from fpga to pc. The configuration is below:
⒈ 100MHz gpif;
2-bit mode "00" & "11" ;
flagb as current thead flag
⒉ FX3 use a multiDMAChannel with 2 producers(Pport0, Pport3) and 1 consumer (Socket1);
16KB buffer size in every DMA channel;
FPGA transfers 16KB data followed by 4B short packet continually, and 1280KB buffer allocated in PC (intel host controller) to receive the data.PC can get all the data correctly every time.
Because of gpif with 2-bit mode , when flagb goes to low (full buffer), fpga must switch another address. Then flagb goes to high(empty buffer).I measure the standing time when flagb keeps low is about 25000clk(0.25ms,10ns every clk, picture below). I think it is too long.
Is the time normal? what causes the long standing time?