A problem about EZ-USB FX3 Slave FIFO | Cypress Semiconductor
A problem about EZ-USB FX3 Slave FIFO
I'm trying to run the example of Slave FIFO in BulkLoop Mode ,but use our Altera FPGA Board. I have some problems with the FlagA & FlagB. Here I set the FlagA & FlagB as Full-Flag and Amost-Full-Flag of Thread_0 which is getting data from FPGA and sending to PC. Here my Fifo databus is 16bit , the watermark of Thread_0 is 6 and the watermark of Thread_3 is 2.
Here is my problems:
1. I find the FlagA & FlagB both high in initial state When I send a text File Out(size 512) through the Control Center. Is that right?
2. Through the waves, I find the FlagA & FlagB doesn't change when Status Machine is running at Bulk_Loop_Write. It cause Status Machine couldn't run to next state. Why FlagA & FlagB doesn't work while FlagC & FlagD work well?
Thank for your help!