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PCLK usage | Cypress Semiconductor

PCLK usage

Summary: 1 Reply, Latest post by aasi on 28 Apr 2012 10:19 PM PDT
Verified Answers: 0
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user_196548820's picture
11 posts

Hi everyone,


Pin 44 of the Samtec expansion connector for the P-port is p_gpio[16] and used as the default synchronous clock for the GPIF II interface.  I was able to measure and confirm this output while modifying the "SlaveFifoAsync" example (adjusted to a 100 MHz output) with the following part of code:


#include "cyu3pib.h"



CyU3PPibClock_t pibClock;
CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;

/* Initialize the p-port block. */
pibClock.clkDiv = 4;
pibClock.clkSrc = CY_U3P_SYS_CLK;
pibClock.isHalfDiv = CyFalse;
/* Disable DLL for sync GPIF */
pibClock.isDllEnable = CyFalse;
apiRetStatus = CyU3PPibInit(CyTrue, &pibClock);



I am now  working on GPIO manipulation and have been using the "GpioApp" example as a starting point.  However I am not able to get the PCLK to output the same signal I was getting before... it isn't outputting anything at all.  I noticed that the "GpioApp" example uses a "gpioClock" and calls the "CyU3PGpioInit" API.  Are these configurations somehow interfering with eachother?  

aasi's picture
Cypress Employee
1166 posts

The PCLK usage case when used with GPIF is different than when you used it as a GPIO. In the case of GPIO you can configure them as complex GPIO and then drive signals on them PWM, one shot etc.

You can configure it as simple GPIO but in your case if you're looking at generating clock signal kind of application then simple GPIO might not serve the purpose.

Please let us know your end application so that we can understand better as to what you're looking for.



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