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Partial full abnormal behavior | Cypress Semiconductor

Partial full abnormal behavior

Summary: 3 Replies, Latest post by kalev on 05 Jan 2015 06:52 AM PST
Verified Answers: 0
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Broccoli's picture
4 posts



I am using 16 bits SlaveFIFO on FX3, PCLK is operate at 100MHz


sending data from FPGA via FX3 to PC


FLAGA is setted as current_thread_full


FLAGB is setted as current_thread_partial_full 


While I monitor FLAGA only, data losses during transmittion. Currently, FLAGB operates normally.




After searching the comments on Forum.


I "ANDed" FLAGA and FLAGB inside FPGA then monitor this signal. But something strange happened...


FLAGB always keep low, no matter how many times I ask data from FX3


Do you guys have any experience or comment on it??


Sorry for the bad image quality, that's all I can get..


Thank you so much for helping!!

Broccoli's picture
4 posts

 one more supplement..

While FLAGB abnormal behavior occurs, FLAGB keeps low, but FLAGA is high.

Since transmision is determined by FLAGA and FLAGB, the abnormal phenomenon will halt the transmission

Broccoli's picture
4 posts

Does any one have the same experience?

If I just monitor FLAGA(full), FLAGB(partial full) function well, but data loss exist.

If I monitor both FLAGA and FLAGB, FLAGB will be assertes randomly regardless of the setting in  watermark.


I had observed that if i stop transmitting data(SLWR pull high) after FLAGB asserted, FLAGB will always keep low and never recover to high state, at the moment FLAGA is still high.


But if I keep writing data regardless of FLAGB, FLAGA will finally goes low and after a while FLAGB recover to high state and then so as FLAGA.


It seems that partial full will recover to high state only when FLAGA is going to recover.


Is there any wrong setting that causes this issue?


P.S. PC is always requesting data from FX3 by cypress streamer (with 64 packets per Xfer and 2 data queues)

kalev's picture
96 posts


FlagB transitioning low indicates that buffer has become almost full. If you stop writing then, buffer actually never becomes full (FlagA remains high).

Every single data item written into GPIF buffer is not transferred to PC immediately. Data remains in GPIF buffer until the GPIF state machine hands the buffer over to USB automata for transferring the data to PC from there.

GPIF state machine submits buffer to USB automata automatically when buffer becomes full. Or, FPGA can force GPIF to submit half-filled/empty buffer by asserting PKTEND signal during write cycle.

So, you should continue to write data until buffer becomes full (FlagA goes low) or assert PKTEND for one write cycle.





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