Partial full abnormal behavior | Cypress Semiconductor
Partial full abnormal behavior
I am using 16 bits SlaveFIFO on FX3, PCLK is operate at 100MHz
sending data from FPGA via FX3 to PC
FLAGA is setted as current_thread_full
FLAGB is setted as current_thread_partial_full
While I monitor FLAGA only, data losses during transmittion. Currently, FLAGB operates normally.
After searching the comments on Forum.
I "ANDed" FLAGA and FLAGB inside FPGA then monitor this signal. But something strange happened...
FLAGB always keep low, no matter how many times I ask data from FX3
Do you guys have any experience or comment on it??
Sorry for the bad image quality, that's all I can get..
Thank you so much for helping!!