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Optimizing throughput on 32 bit FIFO interface | Cypress Semiconductor

Optimizing throughput on 32 bit FIFO interface

Summary: 1 Reply, Latest post by Mudabir Kabir on 19 Mar 2014 01:07 PM PDT
Verified Answers: 1
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kaiyu's picture
49 posts


I've found the AN86947 which shows the optimization for the USBBulkSourceSink image.

It says to work on the combination of burst lenght, dma buffer size and buffer count.

The burst lenght parameter is not present in the SlaveFifoSync image. Can I add it?

Thank you!

Mudabir Kabir's picture
Cypress Employee
44 posts

 Hi Kaiyu,

             Yes. You can use higher burst length to increase throughput if Slave Fifo is reading or writing data from/to external processor/FPGA at huge speeds. 

In SlaveFifoSync example, default burst size of 1 is used. You can alter the line of code to burst length of your choice as follows.

epCfg.burstLen = (usbSpeed == CY_U3P_SUPER_SPEED) ? (CY_FX_EP_BURST_LENGTH) : 1;


Besides this, to maximize throughput in Slave Fifo interface, operate it at maximum frequency of 100 MHz  and setSysClk400 parameter of CyU3PSysClockConfig t must be set to true ( both these are already taken care of in the Slavefifosync firmware)

We have recorded a practical max of 380 Mbytes/s over Slave Fifo interface as against theoretical max of 400 Mbytes/s.

Hope this helps!!


Mudabir Kabir

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