Missing data with Synchronous Fifo Firmware | Cypress Semiconductor
Missing data with Synchronous Fifo Firmware
I am running the synchronous slave fifo firmware in 16 bit GPIF bus mode. I am using an FPGA to write data to the FX3 and to supply the SLWR signal, PCLK at 20 MHZ and monitor FLAGB to determine if the FX3 is full. The FPGA control/data sequence is as follows :
If FLAGB is not asserted the FPGA brings SLWR low and sends an incrementing count over the GPIF data lines to the FX3. As soon as FLAGB goes low the FPGA brings SLWR high and stops incrementing the count. Using the Cypress Control Centre I can view the data transferred from the FPGA to the FX3 over IN endpoint 1. Everything in this transfer seems fine until I cross a 1024 byte boundary where the next packet of 1024 has missed 8 bytes of data. For example if the first 1024 byte packet ended with the count value 1024 instead of seeing the next packet begin with the value 1025 it beings with 1029 - note each count is 2 bytes wide.
I have run the GPIF bus in 32 bit mode and still see the same problem.
Any ideas as to the cause of this?