Mater driving 64K SRAM | Cypress Semiconductor
Mater driving 64K SRAM
I am trying to write a master configuration with 16 bit address and 16 bit data. The GPIF designer allocated the data bus to GPIO 15:0 and the address but to GPIO 49:46 and 27:16. isDQ32Bit is defined as true for IOMatrixConfiguration. For some reason, the upper for address bits located at GPIO49:46 do not seem to reflect the address. Addresses wrap around every 4K of data. Any ideas ? Any similar examples ?