Many to one DMA channels but NOT interleaved buffer? | Cypress Semiconductor
Many to one DMA channels but NOT interleaved buffer?
Is it possible to have AUTO_SIGNAL or AUTO DMA channels for multiple endpoint OUT (data coming from USB port) to one PIB (GPIF-II) socket but the data buffer is NOT interleaved?
I have FX3 GPIF-II attached to FPGA (FX3 is slave, FPGA is master interface) and I am using slave fifo firmware example.
What I want to do is to map several EP-OUT to one PIB socket because I need several of the same data paths from an EP-OUT to GPIF socket. But I want to have 1 dedicated DMA ready flag and 1 dedicated DMA partial flag (not any current thread flag) just like in the slave fifo example.
What I am planning to do is to create several, lets say 2 AUTO DMA channels, one with producer socket is EP1 and consumer socket is PIB socket 0, the other channel is with producer socket is EP2 and consumer socket is PIB socket 0 also.
At first I think this is fine but I am really doubting this..
Any help would be appreciated..