Looking for a firmware example using four endpoints (Sync. FIFO on a FPGA) | Cypress Semiconductor
Looking for a firmware example using four endpoints (Sync. FIFO on a FPGA)
For our design using a FX3 I am looking for a FX3 firmware example using 4 endpoints.
The GPIF II interface is used as a sync. FIFO interface were the FPGA is the master.
The GPIF designer contains a predefined project for this. (sync_slave_fifo_2bit)
The SDK also has a predefined project (SlaveFifoSync), but it seems to only support two endpoints.
Is there a firmware example using four endpoints?
Or is the predefined project easily adapted by just creating two additional endpoints?