J-link (JTAG) schematics | Cypress Semiconductor
J-link (JTAG) schematics
Summary: 3 Replies, Latest post by aasi on 18 Nov 2011 08:13 PM PST
Verified Answers: 0
15 Nov 2011 03:57 PM PST#1
In DVK schematics, pin 15 (N_SRST) is not connected to any pins of FX3.0. However, in the J-Link datasheet, this pin (RESET) is defined to be connected to target CPU reset signal. Is it ok to leave this pin unconnected?