IN_DATA in master mode | Cypress Semiconductor
IN_DATA in master mode
I'm using GPIF at master mode, with CS and WR/RD signal output. The slave will drive data when CS and RD are low at rising edge of PCLK. When the PCLK frequency is below 60MHz, there is no problem. However if the frequency goes higher than 60MHz, the data could not be sampled correctly, due to the delay of slave driving data. Is it possible to output CS and RD at rising edge and sample data at falling edge?