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how to make my project working? | Cypress Semiconductor

how to make my project working?

Summary: 2 Replies, Latest post by jogn_li on 09 Feb 2012 07:26 PM PST
Verified Answers: 0
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jogn_li's picture
49 posts

I use the fx3+fpga and SlaveFifoSync to take some data from pc,but  it did not work.

I use the 0x02 and 0x82 eps in the SlaveFifoSync and A0:A1=0 in my fpga project

#define CY_FX_EP_PRODUCER               0x02    /* EP 1 OUT */
#define CY_FX_EP_CONSUMER               0x82    /* EP 1 IN */

#define CY_FX_PRODUCER_USB_SOCKET    CY_U3P_UIB_SOCKET_PROD_2    /* USB Socket 1 is producer */
#define CY_FX_CONSUMER_USB_SOCKET    CY_U3P_UIB_SOCKET_CONS_2    /* USB Socket 1 is consumer */

/* Used with FX3 Silicon. */
#define CY_FX_PRODUCER_PPORT_SOCKET    CY_U3P_PIB_SOCKET_0    /* P-port Socket 0 is producer */
#define CY_FX_CONSUMER_PPORT_SOCKET    CY_U3P_PIB_SOCKET_3    /* P-port Socket 3 is consumer */

then when I use the Control Center,

Bulk out endpoint (0x02) print is "00000000000.........BULK OUT transfer completed"

Bulk out endpoint(0x82) print is"BULK IN transfer BULK IN transfer failed with Error Code:997"



aasi's picture
Cypress Employee
1166 posts

What are you to send data in the IN direction. Is your FPGA sending data to FX3 or have you just configured it to write always and sending junk data to it?



jogn_li's picture
49 posts

FPGA always send data to fx3,seems fx3 did not know the FPGA at all.

there is any sample to introduce how to use the slavefifo?

the "SlaveFifoSync" in the SDK is working in the RAM and inside,it did not show us how to configure slavefifo receive data from outside.

best regard!!

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