how to make my project working? | Cypress Semiconductor
how to make my project working?
I use the fx3+fpga and SlaveFifoSync to take some data from pc,but it did not work.
I use the 0x02 and 0x82 eps in the SlaveFifoSync and A0:A1=0 in my fpga project,
#define CY_FX_EP_PRODUCER 0x02 /* EP 1 OUT */
#define CY_FX_EP_CONSUMER 0x82 /* EP 1 IN */
#define CY_FX_PRODUCER_USB_SOCKET CY_U3P_UIB_SOCKET_PROD_2 /* USB Socket 1 is producer */
#define CY_FX_CONSUMER_USB_SOCKET CY_U3P_UIB_SOCKET_CONS_2 /* USB Socket 1 is consumer */
/* Used with FX3 Silicon. */
#define CY_FX_PRODUCER_PPORT_SOCKET CY_U3P_PIB_SOCKET_0 /* P-port Socket 0 is producer */
#define CY_FX_CONSUMER_PPORT_SOCKET CY_U3P_PIB_SOCKET_3 /* P-port Socket 3 is consumer */
then when I use the Control Center,
Bulk out endpoint (0x02) print is "00000000000.........BULK OUT transfer completed"
Bulk out endpoint(0x82) print is"BULK IN transfer BULK IN transfer failed with Error Code:997"