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How to generate the interface clock in FX3? | Cypress Semiconductor

How to generate the interface clock in FX3?

Summary: 4 Replies, Latest post by Madhu Sudhan on 26 Mar 2015 03:29 PM PDT
Verified Answers: 0
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luchang's picture
18 posts

 Hi, in my project, it't not easy to generate the PCLK in FPGA , but how can I generate it in FX3?

Thanks a lot.

PRAG's picture
Cypress Employee
173 posts



You would need to set the clock setting in GPIFII Designer to "Internal".

And in firmware, you need to set the parameters of CyU3PPibClock_t structure and pass it in the CyU3PPibInit() API.




Keerthy's picture
Cypress Employee
31 posts

 Hello Luchang,


Please follow the steps mentioned by Shashank to generate PCLK by FX3.

Please make sure that the frequency division factor is adjusted such a way that the PCLK will not exceed 100MHz.




SusieParkins's picture
1 post

Hey there, 


Any one know any simple way to display the pclk frequency via the debugger? I'm finding difficulty in displaying the GPIO[16] freq. 




mady's picture
Cypress Employee
955 posts


If the PCLK is supplied by an external processor to FX3, you cannot display the same's frequency via a Debugger.


- Madhu Sudhan

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