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HOW can the datum flow parallelly | Cypress Semiconductor

HOW can the datum flow parallelly

Summary: 3 Replies, Latest post by 才哥 on 02 Nov 2011 12:29 AM PDT
Verified Answers: 0
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user_87044748's picture
40 posts


Look at the picture, given the producer is GPIF in master mode, the consumer is endpoints for USB, whatever the producer sockets or the consumer sockets, they are both in memory (Sysmem).
The dataflow maybe have 3 steps as below
So question is :
1, In step ②,what make the data flow from producer sockets to consumer sockets?
2,In step ①,to write the data into producer sockets(the secrete Sysmem) , the data pins and address pins are occupied;  in step ② the data pins and address pins are occupied; and so is the step ③。So how can they run parallelly to keep a 100M*32bit throughput.
sorry the picture can't show , so I put it in the attachment
user_87044748's picture
40 posts

 maybe you would say there are no pin in the sysmem , but it is accessed by multiple peripheral block simultaneously. so i can't understand the course.

zirconin's picture
6 posts

 @ Data Flow:

DMA 1 [FIFO -> Socket, DMA Controller, Thread -> DMA-AHB -> Bridge -> ARM-AHB -> Sysmem]

DMA 2 Just the same of DMA 1, chain may reversed.

@ AHB bus freq may be 200MHz @ 32Bits. The 200MHz ARM926 Core hits for that.

@ System Memory can be Accessed by ARM Core, DMA Controllers in Time Divided pattern.

  If the AHB Bus speed and System Memory working freq are high enough, bandwidth is OK.

@ DMA access may use burst mode, please refer SlaveFIFO demo on DMA transfer settings.

  Also, please refer ARM AHB/AXI bus specifications.

@ Data flow is controlled under DMA controller for xfer between Peripheral and Sysmem.

  There may be many DMA controller so that they working in parallel.

  Programmer Manual, DMA section said sth. on this.

@ DMA Controller read descriptor from Sysmem and do data xfer according ot the descriptor.


So please get some ARM core MCU with DMA specs to understand how is DMA working.

And also, ARM official site provide Bus, Core and DMA docs for your reading.

user_87044748's picture
40 posts

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