High speed data acquisition with the EZ-USB-FX3S | Cypress Semiconductor
High speed data acquisition with the EZ-USB-FX3S
I am interested in putting together a high speed data acquisition system. I am looking at the possibility of interfacing a high speed ADC directly to the FX3/FX3S without using an FPGA using for example GPIF.
The ADCs I have been looking at are 14 (or 16) bit quad and octal channel simultaneous sampling ADC devices. Some examples include Linear Technology's LTC2170 14-bit quad ADC family (http://www.linear.com/product/LTC2170-14) and the octal 14-bit LTM9006 ADC family (http://www.linear.com/product/LTM9006-14) each providing sampling rates up to 65 MSPS. The ADCs use serial LVDS output.
I am interested in continuous acquisition at ADC sample rates of at least 10 MSPS per channel and streaming the data directly to a host PC for data storage and analysis. It would be nice to be able to sample at higher sampling rates but in practice there may be some data throughput bandwidth limitations. A quad channel ADC @ 10 MSPS would mean 80 MB/s data throughput., which should be OK. An octal channel at this sampling rate would be 160 MB/s. Trying to stream this to the host PC might cause problems. Having said that the USB3.0 interface should be able to accommodate this data as it theoretically supports a transfer rate of ~ 5 Gbps (625 MB/s) , in practice maybe half this ?
The FX3S offers the possibility of storing data locally on RAID 0 or 1 configured pair of SD/MMC cards. Using UHS-1 , the SanDisk Extreme® PLUS SDXC™ UHS-I card gives values of up 60 MB/s write speed (would realistically/likely be less than this practice, who knows). In a RAID 0 (striped configuration), this could provide in theory up to 120 MB/s write speed. So this may be an alternative for data storage.
I would like to eventually have up to say 32 simultaneous sampling ADC channels. For this I would possibly need to have 4 x FX3S's, each interfaced to an independent USB port on the host PC. I would need to somehow synchronise the ADC clocks to ensure the sampling is simultaneous.
Again I am exploring the option of the above without the use of any FPGA.
I would sincerely appreciate any assistance, feedback etc. as to how I might start to implement- put together a solution for the above.
Thank you in advance,